Configurations are known for respectively converting a plurality of pieces of analog information into digital information and outputting the same. For example, a circuit configuration is known which, in an array processor wherein processor elements (hereinafter PEs) whose result of predetermined processing is referenced as an analog value are mutually connected and arranged, outputs the analog value as a digital value. Analog values to be referenced as a predetermined processing result include, for example, a voltage photoelectrically converted by each pixel cell of a solid-state imaging element (Japanese Patent Laid-Open No. 2005-198149).
In such a configuration, a pixel cell includes: a photo diode as a photoelectric conversion unit; a capacitor as a capacitative element; a comparator as a comparison unit; and a reset switch as a reset unit. In addition, incident light intensity with respect to the pixel cell is referenced as a terminal voltage of the capacitor.
When reading the incident light intensity, a row selection signal line in the solid-state imaging element is selected and a ramp voltage is input from a horizontal signal line. Accordingly, in a solid-state imaging element having pixel cells arranged in a matrix state, incident light intensity of a pixel cell belonging to a row of the matrix is output as a digital signal per each row.
In the conventional technique described above, when obtaining an output signal of a solid-state imaging element constituted by n rows, m columns of pixel cells, processing is executed by inputting a ramp voltage per each row. Therefore, obtaining all values of incident light intensity detected by the solid-state imaging element requires a processing time equal to or exceeding approximately n times the ramp voltage cycle time, resulting in a low operation speed.